Dimmer circuits are commonly used to control power, in particular alternating current (AC) mains power, to a load, such as a light source. In one existing method, a light source can be dimmed using phase controlled dimming whereby power provided to the load is controlled by varying the amount of time that a switch connecting the load to a mains power source is conducting during a cycle of the AC (i.e. varying the duty time). Specifically, AC power to the load is switched ON and OFF during each half cycle of alternating current and the amount of dimming of the load is provided by the amount of ON time in relation to the OFF time for each half cycle.
Phase control dimmer circuits generally operate as trailing edge or leading edge dimmer circuits, and the two circuits are suited to different applications. In leading edge circuits, power is switched OFF at the beginning of each half cycle. In trailing edge circuits, power is switched OFF later in each half cycle (e.g. towards the end of each half cycle). Leading edge dimmer circuits are generally better suited to controlling power to inductive loads, such as small fan motors and iron core low voltage lighting transformers. Trailing edge dimmer circuits, on the other hand, are generally better suited to controlling power to capacitive loads, such as drivers for Light Emitting Diode (LED) lights.
Phase control dimmer circuits, however, can produce conducted harmonics causing electromagnetic interference (EMI) emissions when switching ON and OFF power to the load. Accordingly, existing exemplary phase control dimmer circuits have been configured to produce a more gradual transition between conducting and non-conducting states of the switching circuit to minimise these EMI emissions. For example, in an existing trailing edge dimmer circuit, the turn-OFF transition time of the switch for each half cycle is increased so that power is switched OFF more gradually to the load to reduce the magnitude of associated radio frequency (RF) harmonics produced causing EMI emissions, and thus to minimise line conducted EMI emissions. In trailing edge dimmer circuits, switching OFF of the switching circuit provides greater EMI emissions than switching ON, as switching ON is performed at the zero crossing of the AC. Also, it will be appreciated by those persons skilled in the art that the switching OFF of the switch is performed over a turn-OFF transition time and the switching ON of the switch is performed over a turn-ON transition time. It will be appreciated by those persons skilled in the art that, in an ideal trailing edge dimmer, turn-ON at the zero crossing of the AC implies no associated transition time
Indeed, dimmers with the above-mentioned trailing edge dimmer circuitry are currently sold in many countries that comply with certain regulatory standards for electromagnetic compatibility (EMC) and EMI. Nonetheless, the above mentioned gradual switching OFF of power to the load over an increased turn-OFF transition time results in additional power dissipation for the dimmer circuit switching device. This additional power is generally dissipated as heat by the switching device which can be detrimental to the operation and lifespan of a dimmer employing such a dimmer circuit. Additionally, increased switching losses reduce the achievable maximum load capacity of the dimmer.
Examples of a prior art trailing edge phase control dimmer circuits are shown in FIGS. 1 and 2. Specifically, FIG. 1 shows a prior art trailing edge phase control dimmer circuit 10 with a switching circuit 12 for controlling delivery of AC power to a load (e.g. switching ON and OFF) and a switching control circuit 14 for controlling switching of the switching circuit 12. FIG. 2 shows another prior art trailing edge phase control dimmer circuit 16 with a switching control circuit 18 for controlling switching of the switching circuit 12. The switching control circuit 18 of FIG. 2 also includes the addition of a dv/dt feedback circuit 20 for further controlling switching of the switching circuit 12.
The switching circuit 12, as shown in FIGS. 1 and 2, includes switching elements Q4 and Q5, which are MOSFET switching devices. Specifically, the MOSFETs Q4 and Q5 are high voltage (600V) N-channel MOSFETs (e.g. FCPF11N60), which are used to control the amount of power delivered to the load. The MOSFETs Q4 and Q5 are configured so that they alternately control power delivery to the load over the different polarity half cycles of AC power. That is, the MOSFETs Q4 and Q5 turn-ON and turn-OFF the switching circuit 12 at each cycle of the AC, respectively, so that the load (e.g. a driver for LED down lights) is dimmed in proportion to the amount of time in each cycle that the switching circuit 12 is switched OFF.
The switching control circuit 14 of FIG. 1 and the switching control circuit 18 of FIG. 2 provide gate drive control of the MOSFETs Q4 and Q5. In these examples, the switching control circuits 14 18 exploit a MOSFET's inherent characteristic “Miller Effect” capacitance to control the overall switching time to switch OFF the MOSFETs Q4 and Q5—that is, to control the turn-OFF transition time of the MOSFETs Q4 and Q5. Typical power MOSFETs, like the exemplary power MOSFETs FCPF11N60, that are suitable for trailing edge dimmer circuits, exhibit less than optimum drain-gate capacitance versus drain voltage characteristics which results in a somewhat pronounced non-linearity of provided drain current over a turn-OFF transition due to the rapid fall in the capacitance.
It will be appreciated by those persons skilled in the art that the turn-OFF transition occurs over a time taken to switch OFF, for instance, the MOSFETs Q4 and Q5, hereinafter referred to as “turn-OFF transition time”. It will also be appreciated that, over the turn-OFF transition, the change in MOSFET drain voltage provided by, for instance, the MOSFETs Q4 and Q5 is hereinafter referred to as a “turn-OFF transition profile”.
In order to achieve a low harmonic content and minimise EMI emissions, the rate of change of the slope of the turn-OFF transition profile is to be minimised over the turn-OFF transition. In doing so, however, a longer than optimum overall turn-OFF transition time for power dissipation is typically employed—as provided by the exemplary circuits shown in FIGS. 1 and 2—to ensure that trailing edge phase control dimmer circuits comply with line conducted EMI limits.
The exemplary switching control circuit 14 of FIG. 1, and also the switching control circuit 18 of FIG. 2, implements MOSFET gate drive control using transistors Q1 and Q2. In the examples shown, the transistors Q1 and Q2 are BC856 PNP transistors. Transistor Q1 base drive at resistor R1 input is pulled high to charge MOSFET gate capacitance of the MOSFETs Q4 and Q5 via resistor R2 to hold the MOSFETs Q4 and Q5 in the ON state condition. In the exemplary circuit of FIG. 1, R1 is a 100KΩ resistor and R2 is a 1KΩ resistor. Diode D1 and Zener diode ZD1 are employed to clamp the MOSFETs Q4 and Q5 ON state gate voltage at a suitable level for proper bias. In the examples of FIGS. 1 and 2, D1 is a 4148 high speed diode and ZD1 is a 7V5 Zener diode. Transistor Q2 base drive at R1 input is pulled low to cause discharge of MOSFET gate capacitance via resistor R3, which is of a value that is selected to provide the desired turn-OFF transition time of the MOSFETs Q4 and Q5. R3 is selected as a 56KΩ resistor in the switching control circuit 14 of FIG. 1 to, for example, provide the required turn-OFF transition time of the MOSFETs Q4 and Q5 to comply with EMI requirements.
The turn-OFF transition time provided by the switching control circuit 14 of FIG. 1 is relatively slow using the 56KΩ resistor R3, and is shown in FIG. 4 in a display 40 of an oscilloscope analysing operation of the dimmer circuit 10. As discussed, the relatively slow turn-OFF transition time results in high transition related power dissipation. The display 40 of FIG. 4 shows the load current 42 with 0.5 A per division and MOSFET Q4 and Q5 gate voltage 44 with 2V per division. It will be appreciated by those persons skilled in the art that the load current is indicative of the switching circuit drain voltage when the load has certain impedance characteristics. Specifically, in this example, the load is a resistive load type (e.g. incandescent lamp) so that the load current 42 shown is indicative of the MOSFET Q4 and Q5 drain voltage.
In FIG. 4, it can be seen that the load current 42—indicative of the drain current—is transitioned from the ON to OFF state by the switching control circuit 14 over a turn-OFF transition time of approximately 75 μs. It can also be seen that the load current 42 over the turn-OFF transition forms a curve having a non-linear slope that indicates the turn-OFF transition profile of the dimmer circuit 10 of the prior art circuit exemplified in FIG. 1.
In the exemplary circuit of FIG. 2, the switching control circuit 18 is configured to reduce the turn-OFF transition time by selecting a 22KΩ resistor as R3. It will be appreciated by those persons skilled in the art that turn-OFF transition time can be shortened to reduce transition related power dissipation, but this generally requires a sharper initial turn-OFF and/or a sharper final turn-OFF region of the turn-OFF transition profile which can result in excessive EMI causing harmonics output.
The turn-OFF transition provided by the switching control circuit 14 with a 22KΩ R3 resistor is indicated in FIG. 5 as a display 46 of an oscilloscope analysing operation of this dimmer circuit. The display 46 also shows load current 48 with 0.5 A per division and MOSFET Q4 and Q5 gate voltage 50 with 2V per division. Here, it can be seen that the load current 48 is transitioned from the ON to OFF state over a relatively short turn-OFF transition time of approximately 50 μs. Again, the load current 48 is indicative of the MOSFET Q4 and Q5 drain voltage due to the resistive load being employed for this example. To achieve the relatively short turn-OFF transition time, however, excessive EMI harmonic output is generated by the increased sharpness of the initial/final turn-OFF regions of the turn-OFF transition profile in comparison to the turn-OFF transition profile provided by the switching circuit 14 with a 56KΩ R3 resistor.
Accordingly, existing examples of prior art dimmer circuits have been developed to smooth the initial/final turn-OFF regions of the turn-OFF transition profile to reduce EMI causing harmonics generation of the switching circuit. For example, the switching control circuit 18 of FIG. 2 has a dv/dt feedback circuit 20 to attempt to smooth the initial/final turn-OFF regions of the turn-OFF transition profile to reduce harmonics generation. It will be appreciated by those persons skilled in the art that dv/dt refers to the difference in voltage with respect to the differential in time across the switching element, such as MOSFETs Q4 and Q5.
The dv/dt feedback circuit 20 of FIG. 2 includes a basic drain voltage dv/dt feedback mechanism to reduce the rate of change of the initial/final turn-OFF regions of the turn-OFF transition profile achieved by the switching control circuit 18 having the 22KΩ R3 resistor. The additional operation of the dv/dt feedback circuit 20 of FIG. 2, however, while smoothing the initial/final turn-OFF regions of the turn-OFF transition profile, increases the turn-OFF transition time which causes high associated transition power dissipation of the dimmer circuit 16.
The exemplary turn-OFF transition profile following deployment of the dv/dt feedback circuit 20 of FIG. 2 is indicated in FIG. 6 in a display 52 of an oscilloscope analysing operation of the dimmer circuit 16 with the dv/dt feedback circuit 20. Specifically, the display 52 shows load current 54 with 0.5 A per division and MOSFET Q4 and Q5 gate voltage 56 with 2V per division. Again, in this example, the load current 48 is indicative of the MOSFET Q4 and Q5 drain voltage. Here, it can be seen, however, that, while the initial/final regions of the turn-OFF transition profile are smoother with a more gradual rate of change of slope of the turn-OFF transition profile, the load current 42 is transitioned from the ON to OFF state over a relatively long turn-OFF transition time of approximately 125 μs. In addition, the display 52 shows the dv/dt feedback current 58 with 200 μA per division that is fed to the gate of the MOSFETs Q4 and Q5 of the switching circuit 12.
The dv/dt feedback circuit 20 of FIG. 2 therefore merely employs a basic drain voltage dv/dt feedback mechanism by returning dv/dt feedback current through capacitor C1 with a capacitance that exceeds that required to generate sufficient voltage across resistor R4 to result in operation of transistor Q3 in directing excess dv/dt feedback current to the MOSFETs Q4 and Q5 gate terminal. Since the configuration of the transistor Q3 does not offer any current gain, the regulated dv/dt outcome will remain higher than given by the equation:dv/dt(min)=Vbe(Q3)/(R4×C1).
In the example in FIG. 2, the transistor Q3 is also a BC856 PNP transistor, the capacitor C1 is a 100 pF capacitor, and the resistor R4 is a 3.3KΩ. With reference to the above equation, for example, dv/dt (min)=0.5V/(3.3KΩ×100 pF)=1.5V/μs. Accordingly, in this example, dv/dt corresponds to a transition time of 225 μs at the middle of a half cycle instantaneous voltage of 340V.
Accordingly, the addition of the dv/dt feedback circuit 20 of FIG. 2 to the dimmer circuit 16 still fails to minimise transition power related dissipation which affects the performance and longevity of a dimmer employing the dimmer circuit 16 of FIG. 2.